CDP68HC68T1M【PDF 5/23 页】IC RTC 32X8 NVSRAM CMOS 20-SOIC

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Sheet目录1990

1页 2页 3页 4页 [5页]6页 7页 8页 9页

FN1547.8

October 29, 2007

Watchdog

If this bit is set high, the watchdog circuit has detected a

CPU failure.

Test Mode

When this bit is set high, the device is in the TEST MODE.

First-time Up

Power-on reset sets this bit high. This signifies that data in

the RAM and Clock is not valid and should be initialized.

Interrupt True

A high in this bit signifies that one of the three interrupts

(Power Sense, Alarm, and Clock) is valid.

Power-sense Interrupt

This bit set high signifies that the power-sense circuit has

generated an interrupt.

Alarm Interrupt

When the seconds, minutes and hours time and alarm

counter are equal, this bit will be set high. Status Register

must be read before loading Interrupt Control Register for

valid alarm indication after alarm activates.

Clock Interrupt

A periodic interrupt will set this bit high.

All bits are reset by a power-on reset except the “FIRST-

TIME UP” which is set. All bits except the power-sense bit

are reset after a read of this register.

Pin Signal Description

SCK (Serial Clock Input) (Note 11)

This input causes serial data to be latched from the MOSI

input and shifted out on the MISO output.

MOSI (Master Out/Slave In) (Note 11)

Data bytes are shifted in at this pin, most significant bit

(MSB) first.

MISO (Master In/Slave Out)

Data bytes are shifted out at this pin, most significant bit

(MSB) first.

CE (Chip Enable) (Note 12)

A positive chip-enable input. A low level at this input holds

the serial interface logic in a reset state, and disables the

output driver at the MISO pin.

NOTES:

11. These inputs will retain their previous state if the line driving them

goes into a High-Z state.

12. The CE input has as internal pull-down device, if the input is in a

low state before going to High Z, the input can be left in a High Z.

STATUS REGISTER (Read Only) - Address 30H

WATCHDOG

TEST

MODE

FIRST

TIME

INTERRUPT

TRUE

POWER

SENSE

INTERRUPT

ALARM

INTERRUPT

CLOCK

INTERRUPT

TRUTH TABLE

MODE

SIGNAL

SCK (Note 9)

MOSI

MISO

DISABLE

RESET

INPUT DISABLED

HIGH Z

WRITE

CPOL = 1

CPOL = 0

DATA BIT LATCH

HIGH Z

READ

CPOL = 1

CPOL = 0

NEXT DATA BIT

SHIFTED OUT

(Note 10)

NOTES:

9. When interfacing to CDP68HC05 microcontrollers, serial clock phase bit, CPHA, must be set = 1 in the microcomputer’s Control Register.

10. MISO remains at a high Z until 8-bits of data are ready to be shifted out during a READ. It remains at a high Z during the entire WRITE cycle.

CDP68HC68T1

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